The metal lines over insulators and ground planes, or metal lines buried in close proximity to dielectric insulators and used for integrated circuit interconnects are in reality transmission lines or strip lines. The use of coaxial interconnection lines for interconnections through the substrate in CMOS integrated circuits can also be termed transmission lines or strip lines. Interconnection lines on interposers or printed circuit boards can also be described as transmission lines.
In high density integrated circuits capacitive coupling and mutual inductance between closely packed transmission lines hinders the accuracy of signal detection. Differential transmission lines, with fully differential signals result in much less coupling due to stray capacitance and mutual inductance with other signal, control and/or clock lines. However, as will be shown, differential transmission lines in and of themselves cannot fully alleviate the high density integrated circuit signal detection problem.
Most CMOS integrated circuit interconnections rely on the transmission of a voltage step or signal across transmission lines. The driver on one end of the transmission line may simply be a CMOS inverter and the receiver a simple CMOS amplifier, differential amplifier or comparator. A voltage sense amplifier serving as the CMOS receiver presents a high impedance termination or load to the interconnection line. Most commonly used coaxial transmission lines have an impedance of only 50 ohms or 75 ohms. This fact is problematic for several identifiable reasons. In example, the high impedance termination is troublesome because the switching time response or signal delay is determined mainly by the ability of the driver to charge up the capacitance of the transmission line to neighboring transmission lines or conducting substrates as well as the load capacitance of the voltage sense amplifier. Switching times in CMOS circuits are similarly limited by the ability to switch the capacitive loads of long lines and buffers, and charge these capacitances over large voltage swings to yield a voltage step signal. Also, the transmission line is generally not terminated by its characteristic impedance (i.e. impedance matched) resulting in reflections and ringing. Large noise voltages may be induced on the signal transmission line due to capacitive coupling and large voltage switching on adjacent lines. This noise voltage can in fact be a large fraction of the signal voltage. In CMOS technology, the prior art, for the most part, does not impedance match transmission lines. This is due to the fact that impedance matching low impedance transmission lines is difficult to achieve in CMOS technology.
In contrast, transmission lines are generally impedance matched in ECL circuits. Low impedance resistor terminations are more easily achievable in a bipolar process. The result is that ECL gates have very low input impedances (Zin) looking back into the emitters of the emitter follower inputs (Zin=1/gm). Bipolar transistors have a large transconductance gm=(q/kT) (Idc) determined by the dc emitter current (Idc) so a low impedance is easily achieved, either in matching the sending or receiving end impedances. Matched transmission lines provide better noise immunity with smaller voltage swings on the lines. Unfortunately, ECL circuits consume large amounts of power and are not applicable in a strictly CMOS process.
Similar impedance matched terminations are used in hybrid BiCMOS circuits where bipolar technology resistors are commonly available and can be used for termination. As an example, in high frequency circuits, clock skew can be avoided by using terminated transmission lines for clock synchronization signals. In this example, a BiCMOS technology was utilized and resistors used to provide matching termination on the clock distribution lines. BiCMOS circuits, however, are not applicable to the pure CMOS process steps used in memory circuit fabrication.
The problem remains that it is difficult to impedance match the DRAM voltage sense amplifier to the low characteristic impedance of high speed CMOS transmission lines. Conventionally, impedance matching such transmission lines requires the use of very large width devices. The impedance looking into a CMOS source follower transistor is given by Zin=1/gm. In order to obtain the large values of gm which are needed to yield low input impedances of 50 Ohms, devices with width to length ratios (W/L) on the order of several hundred are necessary. Having such a large width to length ratio not only consumes precious chip surface area but once again increases power requirements.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop improved differential receivers which can be fabricated according to a CMOS process and which can operate at low power supply voltages.